1. Field of the Invention
The present invention generally relates to electrostatic discharge (ESD) protection for integrated circuits (ICs) and, more particularly, to a bi-directional, silicon-controlled rectifier (SCR) arrangement connected between separated power lines of a metal-oxide-semiconductor (MOS) IC to achieve whole-chip ESD protection.
2. Prior Art
As more circuits and functions are integrated into a single semiconductor chip, the chip often needs more power pins to supply sufficient current for circuit operations. For example, a 208-pin CMOS VLSI (very large scale integration) chip may have more than 20 power pins. On the other hand, in mixed mode ICs, the analog power pins are often separated from those of the digital circuits to de-couple the noise from the digital circuits to the analog circuits. Thus, in high performance or high integration CMOS ICs, the power pins of an IC are often separated into many pairs to supply sufficient current for circuit operations or to de-couple noise for better circuit performance. To protect such CMOS ICs with separated power pins and separated power lines from ESD damage in the chip, ESD protection circuits are typically placed around the input and output pads of the IC. However, it has been reported that the interface circuits are more sensitive to ESD damage, even with suitable ESD protection circuits placed around the input and output pads of the IC (see, e.g., M.-D. Ker et al, 1) "ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS ICs," Journal of Microelectronics and Reliability, vol.36, no. 11/12, pp. 1727-1730; 2) "Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins," Proc. of 1994 IEEE International Integrated Reliability Workshop, USA, Oct. 16-19, 1994, pp.124-128; and 3) "Whole-chip ESD protection scheme for CMOS mixed-mode ICs in deep-submicron CMOS technology," Proc. of IEEE Custom Integrated Circuits Conference, Santa Clara, Calif., USA, May 5-8, 1997, pp.31-34).
In addition to the power pins, ESD stress may happen across any two pins of a CMOS IC. The ESD current may enter into the IC through an input pin, and then go out the IC from another input pin or an output pin. So, in the ESD testing standard, i.e., EOS/ESD Standard for ESD Sensitvity Testing, EOS/ESD Association, Inc, N.Y., 1993, pin-to-pin ESD stress has been specified as an ESD-testing condition. In this standard pin-to-pin ESD testing of a chip, positive or negative ESD voltages are applied to one input pin and the other input and output pins are grounded, while the VDD and VSS power pins are floating. This pin-to-pin ESD-testing condition often causes some unexpected ESD damage on the internal circuits lying beyond the input or output ESD protection circuits.
To explain the ESD damage that may occur due to such pin-to-pin ESD stress on a CMOS IC, attention is called to the schematic diagram in FIG. 1, wherein the CMOS IC has two circuits, Circuit I and Circuit II, and a positive ESD voltage is applied to one input pin of Circuit I and an input pin of Circuit II is relatively grounded. In standard pin-to-pin ESD testing, the VDD1, VSS1, VDD2, and VSS2 power lines are all floating. Circuit I has power supplies VDD1 and VSS1, and Circuit II has power supplies VDD2 and VSS2, but, VDD1 is separated from VDD2 and VSS1 is separated from VSS2. Circuits I and II are connected by some interface circuits to transfer the signal message between them in the CMOS IC. This is a typical CMOS IC having two pairs of separated power supply pins. As shown in FIG. 1, when an ESD current, IESD, occurs, it is diverted into the VDD1 power line through the diode Dp1 in the input ESD protection circuit of Circuit I. The ESD current in the VDD1 power line may then flow into the interface circuit through the Mp1 device, at which point, marked as node "A" in FIG. 1, the ESD stress can reach the gate oxide of the Mp3 and Mn3 devices in the interface circuits. Because some of the input pads of Circuit II are grounded, under this pin-to-pin ESD stress, an overstress voltage may be imposed across the gate oxides of the Mp3 and Mn3 devices. Such an overstress voltage across the gate oxides of the Mp3 and Mn3 devices in the interface circuits easily ruptures the gate oxide to cause unexpected ESD damage at the interface circuits while no damage occurs at the input ESD protection circuits. The ESD current discharging path is shown by the dashed lines in FIG. 1. Conversely, FIG. 2 illustrates the ESD current discharging path when the ESD voltage is attached to an input pin of Circuit II and an input pin of the Circuit I is relatively grounded. The ESD voltage is diverted into the VDD2 power line and then goes to the node "B" through the Mp4 device of the interface circuits between the Circuits I and II. The ESD overstress voltage is imposed across and damages the gate oxide of the Mp2 and Mn2 devices in the interface circuits. Thus, the interface circuits between separated power lines in a CMOS IC are endangered by such pin-to-pin ESD stress and the ESD protection circuits around the input pads and output pads can not protect against such unexpected ESD damage at the interface circuits of a CMOS with separated power pins and power lines.
If the power lines in a CMOS IC are not separated, the unexpected ESD damage occurring at the interface circuits of the CMOS does not happen. To achieve a compromise between the requirement of separated power lines and ESD reliability, some prior art ICs have been designed using series diodes to connect the separated power lines. One typical design of such prior art is shown in FIG. 3 (see M.-D. Ker et al, 3) above), and another design to overcome such ESD problems is shown in FIG. 4 (see M.-D. Ker et al, 2) above), where four MOS devices (Mn8, Mn9, Mp10, and Mn11) are used to connect the separated power lines of the CMOS IC in such manner that the ESD stress across the interface circuits can be clamped by the four MOSs. Various shemes using diodes, MOSs, biased junction transistors (BJTs), or field oxide devices (FODs) to connect the separated power lines in a CMOS IC have recently been disclosed in U.S. Pat. Nos. 5,196,981; 5,290,724; 5,301,084; 5,426,323; 5,530,612; 5,610,791; 5,616,943; 5,625,280; and in the Proc. of EOS/ESD Symp., 1993, pp. 239-249; and 1995, pp. 1-20.